rev. 3.3 - 4/29/98 1 1 2 3 4 5 6 7 8 9 10 11 12 features n high-speed access times com?: 10, 12, 15 and 20ns ind?: 12, 15 and 20ns n low power operation (typical) - pdm31256sa active: 200 mw standby: 15mw n single +3.3v ( 0.3v) power supply n ttl-compatible inputs and outputs n packages plastic soj (300 mil) - so plastic tsop (i) - t description the pdm31256 is a high-performance cmos static ram organized as 32,768 x 8 bits. writing to this device is accomplished when the write enable (we ) and the chip enable (ce ) inputs are both low. reading is accomplished when we remains high and ce and oe are both low. the pdm31256 operates from a single +3.3v power supply and all the inputs and outputs are fully ttl- compatible. the pdm31256 is available in a 28-pin 300-mil plastic soj and a 28-pin plastic tsop (i). a a 0 14 i/o i/o 0 7 ce we addresses decoder memory matrix input data control column i/o oe control functional block diagram pdm31256 3.3v 256k static ram 32k x 8-bit
pdm31256 2 rev. 3.3 - 4/29/98 oe
a11
a9
a8
a13
we
vcc
a14
a12
a7
a6
a5
a4
a3
21
20
19
18
17
16
15
14
13
12
11
10
9
8 a10
ce
i/o7
i/o6
i/o5
i/o4
i/o3
vss
i/o2
i/o1
i/o0
a0
a1
a2 22
23
24
25
26
27
28
1
2
3
4
5
6
7 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 a14
a12
a7
a6
a5
a4
a3
a2
a1
a0
i/o0
i/o1
i/o2
vss vcc
we
a13
a8
a9
a11
oe
a10
ce
i/o7
i/o6
i/o5
i/o4
i/o3 13 14 25 26 27 28 truth table note: 1. h = v ih , l = v il , x = don? care absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect reliability. 2. appropriate thermal calculations should be performed in all cases and speci?ally for those where the chosen package has a large thermal resistance (e.g., tsop). the calculation should be of the form : t j = t a + p * q ja where t a is the ambient tempera- ture, p is average operating power and q ja the thermal resistance of the package. for this product, use the following q ja values: soj: 78 o c/w tsop: 112 o c/w oe we ce i/o mode x x h hi-z standby lhld out read xlld in write h h l hi-z output disable symbol rating com l. ind. unit v term terminal voltage with respect to vss ?.5 to +4.6 ?.5 to +4.6 v t bias temperature under bias ?5 to +125 ?5 to +135 c t stg storage temperature ?5 to +125 ?5 to +150 c p t power dissipation 1.0 1.0 w i out dc output current 50 50 ma t j maximum junction temperature (2) 125 145 c pin con?urations tsop soj pin description name description a14-a0 address inputs i/o7-i/o0 data inputs/outputs oe output enable input we write enable input ce chip enable input v cc power (+3.3v) v ss ground
pdm31256 rev. 3.3 - 4/29/98 3 1 2 3 4 5 6 7 8 9 10 11 12 recommended dc operating conditions dc electrical characteristics (v cc = 3.3v 0.3v) note:1.v il (min) = ?.0v for pulse width less than 20 ns. power supply characteristics notes: all values are maximum guaranteed values. symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v v ss supply voltage 0 0 0 v commercial ambient temperature 0 25 70 c industrial ambient temperature ?0 25 85 c symbol parameter test conditions min. max. unit i li input leakage current v cc = max., v in = vss to v cc ? 5 m a i lo output leakage current v cc = max., ce = v ih , v out = vss to v cc ? 5 m a v il input low voltage ?.3 (1) 0.8 v v ih input high voltage 2.2 vcc+0.3 v v ol output low voltage i ol = 8 ma v cc = min. 0.4 v v oh output high voltage i oh = ? ma, v cc = min. 2.4 v -10 -12 -15 -17 -20 symbol parameter com l. com l ind. com l ind. com l ind. com l ind. unit i cc operating current ce = v il 140 130 130 120 120 120 120 110 110 ma f = f max = 1/t rc v cc = max. i out = 0 ma i sb standby current ce = v ih 45 40 35 35 35 35 35 30 30 ma f = f max = 1/t rc v cc = max. i sb1 full standby current ce 3 v cc ?0.2v 10 10 15 10 15 10 15 10 15 ma f = 0 v cc = max., v in 3 v cc ?0.2v or 0.2v
pdm31256 4 rev. 3.3 - 4/29/98 capacitance (1) (t a = +25 c, f = 1.0 mhz) note: 1. this parameter is determined by device characterization but is not production tested. ac test conditions symbol parameter max. unit c in input capacitance 8 pf c out output capacitance 8 pf input pulse levels v ss to 3.0v input rise and fall times 2.5 ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 figure 1. output load equivalent figure 2. output load equivalent (for t lzce , t hzce , t lzwe , t hzwe , t lzoe , t hzoe ) 353 w 319 w 30 pf +3.3v data out 353 w 319 w 5 pf +3.3v data out 5 4 3 2 1 0 0 30 60 90 120 typical delta t aa vs capacitive loading additional lumped capacitive loading (pf) delta t aa - ns figure 3.
pdm31256 rev. 3.3 - 4/29/98 5 1 2 3 4 5 6 7 8 9 10 11 12 read cycle no. 1 (1) read cycle no. 2 (2) ac electrical characteristics description -10 -12 -15 -17 -20 read cycle sym min. max. min. max. min. max. min max min max units read cycle time t rc 10 12 15 17 20 ns address access time t aa 10 12 15 17 20 ns chip enable access time t ace 10 12 15 17 20 ns output hold from address change t oh 333 33 ns chip enable to output in low z (3,4,5) t lzce 555 55 ns chip disable to output in high z (3,4,5) t hzce 81010 12 15 ns chip enable to power up time (4) t pu 000 00 ns chip disable to power down time (4) t pd 10 12 15 17 20 ns output enable access time t aoe 568 910 ns output enable to output in low z (4,5) t lzoe 000 00 ns output disable to output in high z (4,5) t hzoe 888 88 ns t rc t aa t oh previous data valid d out addr data valid t rc t ace t aa t lzce t hzce t lzoe t hzoe t aoe addr ce oe d out data valid
pdm31256 6 rev. 3.3 - 4/29/98 write cycle no. 1 (write enable controlled) write cycle no. 2 (chip enable controlled) ac electrical characteristics description -10 -12 -15 -17 -20 write cycle sym min. max. min. max. min. max. min. max. min. max. units write cycle time t wc 10 12 15 17 20 ns chip enable to end of write t cw 10 10 12 12 13 ns address valid to end of write t aw 10 10 12 12 13 ns address setup time t as 000 00 ns address hold from end of write t ah 000 00 ns write pulse width t wp 81011 11 12 ns data setup time t ds 777 89 ns data hold time t dh 000 00 ns write disable to output in low z (4,5) t lzwe 000 00 ns write enable to output in high z (4,5) t hzwe 333 33 ns t wc t aw t cw t ah t as t hzwe high z data valid t lzwe t ds t dh addr ce t wp we d in d out t wc t aw t cw t wp t ds data valid t dh t as addr d in undefined don't care t ah ce we
pdm31256 rev. 3.3 - 4/29/98 7 1 2 3 4 5 6 7 8 9 10 11 12 notes: (for two previous electrical characteristics tables) 1. the device is continuously selected. chip enable is held in its active state. 2. the address is valid prior to or coincident with the latest occuring chip enable. 3. at any given temperature and voltage condition, t hzce is less than t lzce . 4. this parameter is sampled. 5. the parameter is tested with cl = 5 pf as shown in figure 2. transition is measured 200 mv from steady state voltage. ordering information device type power speed package type process temp. range preferred shipping container commercial (0 to +70 c) industrial (?0 c to +85 c) 10 commercial only 12 15 17 20 sa standard power blank i a automotive ( ?0 c to +105 c) blank tubes tr tape & reel ty tray pdm31256 - 256k (32kx8) sync. static ram xxxxx x xx x x x so 28-pin 300-mil plastic soj t 28-pin plastic tsop (i) faster memories for a fasterworld
|
